1. Field
The present disclosure generally relates to techniques for designing and manufacturing integrated circuits (ICs). More specifically, the present disclosure relates to techniques and systems for accurately and efficiently modeling thin-film stack topography effect on a photolithography process.
2. Related Art
Dramatic improvements in semiconductor integration circuit (IC) technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor IC chip. These improvements in integration densities have largely been achieved through corresponding improvements in semiconductor manufacturing technologies. Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to find exact formulae to predict the behavior of these complex interactions, developers typically use process models which are fit to empirical data to predict the behavior of these processes. A process model can be used in a number of applications during the design of a semiconductor chip.
For example, in a technique which is referred to as “optical proximity correction” (OPC), a photolithography process model (hereinafter “lithography model”) is used to make corrections to a semiconductor chip layout to compensate for undesirable effects of semiconductor manufacturing processes. During an OPC process, an OPC simulation engine uses the lithography model to iteratively evaluate and modify edge segments in the mask layout. The post-OPC mask patterns are expected to produce physical patterns on the wafer that closely match design intent.
Note that the accuracy of the lithography model can limit both the effectiveness of corrected mask patterns and the correctness of post-OPC design layout verification. As Moore's law drives IC features to increasingly smaller dimensions (which are now below 45 nm), certain physical effects, which have been largely ignored or oversimplified in existing lithography models, are becoming increasingly important for lithography model accuracy. Hence, it is desirable to provide more comprehensive, physics-centric descriptions for these physical effects to improve the lithography model accuracy.
In particular, topography variation within a multilayer thin-film structure on a wafer is one of the physical effects that are inadequately represented in a conventional lithography model. During the semiconductor fabrication process, each patterned thin-film layer (or “patterned layer”) is typically not planar but has topography variations caused by the pattern features within the thin-film layer. When a patterned layer is subsequently coated with photoresist in order to fabricate a new layer, the surface topography profile of the patterned layer becomes an “underlying” topography profile. Hence, in a multilayer thin-film stack, multiple underlying topography profiles, which typically differ from each other, exist at different depths underneath the wafer surface. Unfortunately, conventional lithography models can lead to serious defects caused by ignoring or oversimplifying the underlying topography effect. For example, it is noticed that when using such a conventional lithography model, pinching or breaking in implant layer resist lines can occur as a result of the topography effect from underlying shallow trench isolation (STI) layer and poly-gate layer.
Note that performing a rigorous lithography simulation of each underlying topography layer is often impractical because it can require days of computation time to compute the topography effect just for a very small wafer area. Hence, there is a need for efficient techniques and systems for accurately modeling the underlying thin-film topography effect on the lithography process without the above-described problems.